To enhance performance, a processor can employ multithreading whereby one or more executing programs are separated into multiple threads that are executed at an instruction pipeline of the processor. To further enhance performance, the processor can be configured so that the multiple threads can share one or more stages of the instruction pipeline. For each cycle of the instruction pipeline each of the shared units individually selects one of the multiple threads for processing according to a fixed selection scheme, such as a round robin scheme. However, such a fixed selection scheme can be inefficient when the multiple threads have differing needs for processor resources.
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